Regviz

Silicon Labs /EFR32FG23A010F512GM40 /GPIO_NS /PRS0_ROUTEEN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PRS0_ROUTEEN

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32BG22C222F352GM40/GPIO_NS/PRS0_ROUTEEN#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ASYNCH0PEN)ASYNCH0PEN 0 (ASYNCH1PEN)ASYNCH1PEN 0 (ASYNCH2PEN)ASYNCH2PEN 0 (ASYNCH3PEN)ASYNCH3PEN 0 (ASYNCH4PEN)ASYNCH4PEN 0 (ASYNCH5PEN)ASYNCH5PEN 0 (ASYNCH6PEN)ASYNCH6PEN 0 (ASYNCH7PEN)ASYNCH7PEN 0 (ASYNCH8PEN)ASYNCH8PEN 0 (ASYNCH9PEN)ASYNCH9PEN 0 (ASYNCH10PEN)ASYNCH10PEN 0 (ASYNCH11PEN)ASYNCH11PEN 0 (SYNCH0PEN)SYNCH0PEN 0 (SYNCH1PEN)SYNCH1PEN 0 (SYNCH2PEN)SYNCH2PEN 0 (SYNCH3PEN)SYNCH3PEN

Description

PRS0 pin enable

Fields

ASYNCH0PEN

ASYNCH0 pin enable control bit
ASYNCH1PEN

ASYNCH1 pin enable control bit
ASYNCH2PEN

ASYNCH2 pin enable control bit
ASYNCH3PEN

ASYNCH3 pin enable control bit
ASYNCH4PEN

ASYNCH4 pin enable control bit
ASYNCH5PEN

ASYNCH5 pin enable control bit
ASYNCH6PEN

ASYNCH6 pin enable control bit
ASYNCH7PEN

ASYNCH7 pin enable control bit
ASYNCH8PEN

ASYNCH8 pin enable control bit
ASYNCH9PEN

ASYNCH9 pin enable control bit
ASYNCH10PEN

ASYNCH10 pin enable control bit
ASYNCH11PEN

ASYNCH11 pin enable control bit
SYNCH0PEN

SYNCH0 pin enable control bit
SYNCH1PEN

SYNCH1 pin enable control bit
SYNCH2PEN

SYNCH2 pin enable control bit
SYNCH3PEN

SYNCH3 pin enable control bit

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data